Low Power Digital Multimedia Telecommunication Designs
نویسندگان
چکیده
منابع مشابه
Trends in Low Power Digital System-on-Chip Designs (invited)
A study of the future trends in low-power System-on-Chip (SOC) designs is presented, based on the recently announced ITRS-2001 technology characteristics for both highperformance and low-power devices from 2001 to 2016. We forecast the logic/memory composition of a reference low-power PDA design with an area constraint of 1cm using both a bottom-up, power dissipation-constrained chip model and ...
متن کاملLow-power Multimedia Dsp Systems
Keshab K. Parhi Department of Electrical and Computer Engineering University of Minnesota, Minneapolis, MN 55455, USA E-mail: [email protected] Abstract In a few years, multimedia will become part of everyone's life. This paper presents an overview of DSP processors which are targeted for multimedia applications. Current and future trends of these processors are predicted. Reduction of power co...
متن کاملCircuit Designs for Low-power and Seu- Hardened Systems Circuit Designs for Low-power and Seu- Hardened Systems Vii Circuit Designs for Low-power and Seu-hardened Systems
OF THESIS Submitted in Partial Fulfillment of the Requirements for the Degree of Master of Science Electrical Engineering The University of New Mexico Albuquerque, New Mexico
متن کاملPLA Minimization for Low Power VLSI Designs
In this paper we study the problem of optimizing the two-level representation of a Boolean function in order to minimize power consumption in PLAs. We first give power models used to estimate the power consumption in pseudo-NMOS and dynamic PLAs. Using these power cost functions we then prove that a minimum power solution for dynamic PLAs consists only of prime implicants of the function. For p...
متن کاملHigh-Speed Low-Power Small-Area Accumulator Designs for Direct Digital Frequency Synthesizers
This paper presents high-speed low-power small-area accumulator designs to be used in DDFS systems. To reduce the Numerically Controlled Oscillator (NCO) design complexity and size, only the most significant bits of the accumulator drive the phase to amplitude mapping block. Those bits need to be updated on every sampling clock, while the least significant bits of the accumulator are not visibl...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
ژورنال
عنوان ژورنال: VLSI Design
سال: 2001
ISSN: 1065-514X,1563-5171
DOI: 10.1155/2001/43078